Field of the Invention
The invention relates in general to a memory self-testing device and method, and more particularly to a memory self-testing device and method for testing whether channels and memory control units of a memory are functional.
Description of the Related Art
FIG. 1 shows a block diagram of a conventional circuit system including a memory self-testing device. For example, the circuit system 100 is a partial circuit of a digital television system, and includes a memory self-testing device 110, a plurality of client ends 120, a bus 130, a plurality of channels 140, a plurality of memory control units (e.g., memory interface units, MIUs) 150, and a plurality of memory components 160. Each client end 120 is a function module of the television system 100, e.g., a Universal Serial Bus (USB) control unit, and accesses the memory components in an operation period. Each client end 120 may select one of the channels 140 via the bus 130 to access that memory component 160 with the memory control unit 150. To ensure that each client end 120 is capable of smoothly accessing the memory component 160 to complete its function, after the circuit system 100 is activated and starts normal operations, the channels 140 and the memory control units 150 are individually tested by the memory self-testing device 110. During the test, one channel 140 and the corresponding memory control unit 150 are first selected, and predetermined data is generated and written into the memory component 160 via the selected channel 140 and memory control unit 150. Data in the memory component 160 is read and compared with the written data to determine if the two sets of data are the same. If so, it means that the selected channel 140 and channel control unit 150 are normal, or else they are abnormal. As such, the test for one channel 140 and one memory control unit 150 is complete. If the circuit system 100 includes N channels 140 and N memory control units 150, the above steps need to be performed for N times to complete the test for all the channels and memory control units. Such time-consuming process results in an excessively long activation time.
FIG. 2 shows a block diagram of a conventional circuit system including a plurality of memory self-testing devices. FIG. 2 is an improvement of the circuit system 100 in FIG. 1. To reduce the activation time, the circuit system 200 includes multiple memory self-testing devices 110, which may simultaneously test multiple channels 140 and multiple control units 150. Thus, the activation time of the circuit system 200 is noticeably reduced, with however circuit costs being significantly increased as a trade-off.